ORCID: 0009-0007-5419-206X
Email: ydtsen@ieee.org
🎯 Careers
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Industry Mentor, Department of Industrial Management
National Taiwan University of Science and Technology (NTUST)
2024~now -
Manager of Intelligent Manufacturing Center
Taiwan Semiconductor Manufacturing Company (TSMC)
2007~2022 (retired)
📚 Publications & Patents
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"Integrated Hierarchical Reinforcement Learning for Enhanced CMP Manufacturing Efficiency."
PriMera Scientific Engineering, Vol. 9, Issue 1, pp. 11-21, July 2026
DOI: 10.56831/PSEN-09-279 -
"Deep Hierarchical Reinforcement Learning CMP Run to Run Control."
International Conference on Flexible Automation and Intelligent Manufacturing. Cham: Springer Nature Switzerland, 2024. -
"Reinforcement learning chemical-mechanical polishing run-to-run controller."
2023 IEEE 5th Eurasia Conference on IoT, Communication and Engineering (ECICE). IEEE, 2023. -
"Predictive control of quality in batch polymerization using hybrid ANN models."
AIChE Journal 42.2 (1996): 455-465. -
System and method for implementing a virtual metrology advanced process control platform
US patent: US-8437870-B2, 2013 -
System and method for implementing multi-resolution advanced process control
US patent: US-8394719-B2, 2013 -
Method and system for implementing virtual metrology in semiconductor fabrication
US patent: US-8396583-B2, 2013 -
Advanced process control with novel sampling policy
US patent: US-8392009-B2, 2013 -
Advanced process control for new tapeout product
US patent: US-8239056-B2, 2012 -
Method and system for tuning advanced process control parameters
US patent: US-8229588-B2, 2012 -
Method and apparatus for advanced process control
US patent: US-8224475-B2, 2012 -
System and method for implementing wafer acceptance test ("WAT") advanced process control ("APC") with routing model
US patent: US-8219341-B2, 2012 -
System and method for implementing a wafer acceptance test ("WAT") advanced process control ("APC") with novel sampling policy and architecture
US patent: US-8108060-B2, 2012 -
Method for a bin ratio forecast at new tape out stage
US patent: US-8082055-B2, 2011 -
Method for bin-based control
US patent: US-8041451-B2, 2011 -
Method and system for implementing virtual metrology in semiconductor fabrication
US patent: US-20110238198-A1, 2011 -
System and method for implementing multi-resolution advanced process control
US patent: US-20110213478-A1, 2011 -
System and method for implementing multi-resolution advanced process control
US patent: US-7951615-B2, 2011 -
Advanced process control for new tapeout product
US patent: US-20110112678-A1, 2011 -
Method for a bin ratio forecast at new tape out stage
US patent: US-20110010215-A1, 2011 -
System and method for implementing a virtual metrology advanced process control platform
US patent: US-20100312374-A1, 2010 -
System and method for implementing a wafer acceptance test ("WAT") advanced process control ("APC") with novel sampling policy and architecture
US patent: US-20100292824-A1, 2010 -
Method for bin-based control
US patent: US-20100268367-A1, 2010 -
System and method for implementing multi-resolution advanced process control
US patent: US-20100255613-A1, 2010 -
System and method for implementing wafer acceptance test ("WAT") advanced process control ("APC") with routing model
US patent: US-20100250172-A1, 2010 -
Advanced process control with novel sampling policy
US patent: US-20100249974-A1, 2010 -
Method and apparatus for advanced process control
US patent: US-20100234970-A1, 2010 -
Method and system for tuning advanced process control parameters
US patent: US-20100228370-A1, 2010